canlinsbc.h

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/****************************************************************************
** Copyright (C) 2020 MikroElektronika d.o.o.
** Contact: https://www.mikroe.com/contact
**
** Permission is hereby granted, free of charge, to any person obtaining a copy
** of this software and associated documentation files (the "Software"), to deal
** in the Software without restriction, including without limitation the rights
** to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
** copies of the Software, and to permit persons to whom the Software is
** furnished to do so, subject to the following conditions:
** The above copyright notice and this permission notice shall be
** included in all copies or substantial portions of the Software.
**
** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
**  USE OR OTHER DEALINGS IN THE SOFTWARE.
****************************************************************************/

 
#ifndef CANLINSBC_H
#define CANLINSBC_H
 
#ifdef __cplusplus
extern "C"{
#endif

#ifdef PREINIT_SUPPORTED
#include "preinit.h"
#endif
 
#ifdef MikroCCoreVersion
    #if MikroCCoreVersion >= 1
        #include "delays.h"
    #endif
#endif
 
#include "drv_digital_out.h"
#include "drv_digital_in.h"
#include "drv_uart.h"
#include "drv_spi_master.h"
#include "spi_specifics.h"




#define CANLINSBC_REG_DMCR                      0x01
#define CANLINSBC_REG_LDOCR                     0x02
#define CANLINSBC_REG_DMSR                      0x03
#define CANLINSBC_REG_SECR                      0x04
#define CANLINSBC_REG_LDOECR                    0x05
#define CANLINSBC_REG_GPM0                      0x06
#define CANLINSBC_REG_GPM1                      0x07
#define CANLINSBC_REG_GPM2                      0x08
#define CANLINSBC_REG_GPM3                      0x09
#define CANLINSBC_REG_RWPR                      0x0A
#define CANLINSBC_REG_TRXCR                     0x20
#define CANLINSBC_REG_LTRXCR                    0x21
#define CANLINSBC_REG_TRXSR                     0x22
#define CANLINSBC_REG_TRXECR                    0x23
#define CANLINSBC_REG_LTRXSR                    0x24
#define CANLINSBC_REG_REGCR                     0x25
#define CANLINSBC_REG_DRCR                      0x26
#define CANLINSBC_REG_CIDR0                     0x27
#define CANLINSBC_REG_CIDR1                     0x28
#define CANLINSBC_REG_CIDR2                     0x29
#define CANLINSBC_REG_CIDR3                     0x2A
#define CANLINSBC_REG_CIDMR0                    0x2B
#define CANLINSBC_REG_CIDMR1                    0x2C
#define CANLINSBC_REG_CIDMR2                    0x2D
#define CANLINSBC_REG_CIDMR3                    0x2E
#define CANLINSBC_REG_CFCR                      0x2F
#define CANLINSBC_REG_BFECR                     0x32
#define CANLINSBC_REG_BFIR                      0x33
#define CANLINSBC_REG_TRXECR2                   0x34
#define CANLINSBC_REG_TRXESR2                   0x35
#define CANLINSBC_REG_WDCR1                     0x36
#define CANLINSBC_REG_WDCR2                     0x37
#define CANLINSBC_REG_WDSR                      0x38
#define CANLINSBC_REG_WDTRIG                    0x39
#define CANLINSBC_REG_EFCR                      0x3A
#define CANLINSBC_REG_FECR                      0x3B
#define CANLINSBC_REG_GLFT                      0x67
#define CANLINSBC_REG_CDMR0                     0x68
#define CANLINSBC_REG_CDMR1                     0x69
#define CANLINSBC_REG_CDMR2                     0x6A
#define CANLINSBC_REG_CDMR3                     0x6B
#define CANLINSBC_REG_CDMR4                     0x6C
#define CANLINSBC_REG_CDMR5                     0x6D
#define CANLINSBC_REG_CDMR6                     0x6E
#define CANLINSBC_REG_CDMR7                     0x6F
#define CANLINSBC_REG_PWKS                      0x4B
#define CANLINSBC_REG_WKECR                     0x4C
#define CANLINSBC_REG_GESR                      0x60
#define CANLINSBC_REG_SESR                      0x61
#define CANLINSBC_REG_LTRXESR                   0x62
#define CANLINSBC_REG_CTRXESR                   0x63
#define CANLINSBC_REG_WKESR                     0x64
#define CANLINSBC_REG_BFESR                     0x65
#define CANLINSBC_REG_LDOESR                    0x66
#define CANLINSBC_REG_DIDR                      0x7E
 // canlinsbc_reg



#define CANLINSBC_DMCR_RSTEN                    0x20
#define CANLINSBC_DMCR_VCCOVSD                  0x10
#define CANLINSBC_DMCR_SLPVCCUC                 0x08
#define CANLINSBC_DMCR_DOPM_SLEEP_MODE          0x01
#define CANLINSBC_DMCR_DOPM_STANDBY_MODE        0x04
#define CANLINSBC_DMCR_DOPM_NORMAL_MODE         0x07
#define CANLINSBC_DMCR_DOPM_MASK                0x07

#define CANLINSBC_TRXCR_CFDPE                   0x40
#define CANLINSBC_TRXCR_PNCFOK                  0x20
#define CANLINSBC_TRXCR_CPNE                    0x10
#define CANLINSBC_TRXCR_COMP_STANDBY_MODE       0x00
#define CANLINSBC_TRXCR_COMP_NORMAL_MODE        0x01
#define CANLINSBC_TRXCR_COMP_SILENT_MODE        0x03
#define CANLINSBC_TRXCR_COMP_MASK               0x03

#define CANLINSBC_WDCR1_WDC_OFF_MODE            0x20
#define CANLINSBC_WDCR1_WDC_TIME_OUT_MODE       0x40
#define CANLINSBC_WDCR1_WDC_WINDOW_MODE         0x80
#define CANLINSBC_WDCR1_WDC_MASK                0xE0
#define CANLINSBC_WDCR1_WDPRE_FACTOR_1          0x00
#define CANLINSBC_WDCR1_WDPRE_FACTOR_1_5        0x08
#define CANLINSBC_WDCR1_WDPRE_FACTOR_2_5        0x10
#define CANLINSBC_WDCR1_WDPRE_FACTOR_3_5        0x18
#define CANLINSBC_WDCR1_WDPRE_MASK              0x18
#define CANLINSBC_WDCR1_WDLSP                   0x04
#define CANLINSBC_WDCR1_WDLW                    0x02

#define CANLINSBC_WDTRIG_RESET                  0x55

#define CANLINSBC_DEVICE_ID                     0x86

#define CANLINSBC_SET_DATA_SAMPLE_EDGE          SET_SPI_DATA_SAMPLE_EDGE
#define CANLINSBC_SET_DATA_SAMPLE_MIDDLE        SET_SPI_DATA_SAMPLE_MIDDLE

#define CANLINSBC_TX_DRV_BUFFER_SIZE            100
#define CANLINSBC_RX_DRV_BUFFER_SIZE            300
 // canlinsbc_set



#define CANLINSBC_MAP_MIKROBUS( cfg, mikrobus ) \
    cfg.miso = MIKROBUS( mikrobus, MIKROBUS_MISO ); \
    cfg.mosi = MIKROBUS( mikrobus, MIKROBUS_MOSI ); \
    cfg.sck  = MIKROBUS( mikrobus, MIKROBUS_SCK ); \
    cfg.cs   = MIKROBUS( mikrobus, MIKROBUS_CS ); \
    cfg.rst  = MIKROBUS( mikrobus, MIKROBUS_RST ); \
    cfg.txd_lin = MIKROBUS( mikrobus, MIKROBUS_PWM ); \
    cfg.rxd_lin = MIKROBUS( mikrobus, MIKROBUS_INT ); \
    cfg.tx_pin  = MIKROBUS( mikrobus, MIKROBUS_TX ); \
    cfg.rx_pin  = MIKROBUS( mikrobus, MIKROBUS_RX );
 // canlinsbc_map // canlinsbc

typedef struct
{
    // Output pins
    digital_out_t rst;          
    digital_out_t txd_lin;      
 
    // Input pins
    digital_in_t rxd_lin;       
 
    // Modules
    spi_master_t spi;           
 
    // Modules
    uart_t uart;                
 
    // Buffers
    uint8_t uart_rx_buffer[ CANLINSBC_RX_DRV_BUFFER_SIZE ];  
    uint8_t uart_tx_buffer[ CANLINSBC_TX_DRV_BUFFER_SIZE ];  
 
    pin_name_t chip_select;     
 
} canlinsbc_t;

typedef struct
{
    // Communication gpio pins
    pin_name_t miso;            
    pin_name_t mosi;            
    pin_name_t sck;             
    pin_name_t cs;              
    pin_name_t rx_pin;          
    pin_name_t tx_pin;          
 
    // Additional gpio pins
    pin_name_t rst;             
    pin_name_t txd_lin;         
    pin_name_t rxd_lin;         
 
    // static variable
    uint32_t                          spi_speed;    
    spi_master_mode_t                 spi_mode;     
    spi_master_chip_select_polarity_t cs_polarity;  
    uint32_t         baud_rate;                     
    bool             uart_blocking;                 
    uart_data_bits_t data_bit;                      
    uart_parity_t    parity_bit;                    
    uart_stop_bits_t stop_bit;                      
 
} canlinsbc_cfg_t;

typedef enum
{
    CANLINSBC_OK = 0,
    CANLINSBC_ERROR = -1
 
} canlinsbc_return_value_t;


void canlinsbc_cfg_setup ( canlinsbc_cfg_t *cfg );

err_t canlinsbc_init ( canlinsbc_t *ctx, canlinsbc_cfg_t *cfg );

err_t canlinsbc_default_cfg ( canlinsbc_t *ctx );

err_t canlinsbc_write_reg ( canlinsbc_t *ctx, uint8_t reg, uint8_t data_in );

err_t canlinsbc_read_reg ( canlinsbc_t *ctx, uint8_t reg, uint8_t *data_out );

err_t canlinsbc_generic_write ( canlinsbc_t *ctx, uint8_t *data_in, uint16_t len );

err_t canlinsbc_generic_read ( canlinsbc_t *ctx, uint8_t *data_out, uint16_t len );

void canlinsbc_set_rst_pin ( canlinsbc_t *ctx, uint8_t state );

void canlinsbc_set_txd_lin_pin ( canlinsbc_t *ctx, uint8_t state );

uint8_t canlinsbc_get_rxd_lin_pin ( canlinsbc_t *ctx );

void canlinsbc_reset_device ( canlinsbc_t *ctx );

err_t canlibsbc_check_communication ( canlinsbc_t *ctx );
 
#ifdef __cplusplus
}
#endif
#endif // CANLINSBC_H
 // canlinsbc
 
// ------------------------------------------------------------------------ END